Vrudhula, Sarma B. K.: search on Z-Library

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1

[ACM Press the 2017 ACM/SIGDA International Symposium - Monterey, California, USA (2017.02.22-2017.02.24)] Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '17 - Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks

Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

Year:

2017

Language:

english

File:

PDF, 517 KB

english, 2017

2

[ACM Press the 2016 ACM/SIGDA International Symposium - Monterey, California, USA (2016.02.21-2016.02.23)] Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - FPGA '16 - Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks

Suda, Naveen, Chandra, Vikas, Dasika, Ganesh, Mohanty, Abinash, Ma, Yufei, Vrudhula, Sarma, Seo, Jae-sun, Cao, Yu

Year:

2016

Language:

english

File:

PDF, 607 KB

english, 2016

3

Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 3.94 MB

english, 2018

4

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Kulkarni, Niranjan, Yang, Jinghua, Seo, Jae-Sun, Vrudhula, Sarma

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2016

Language:

english

File:

PDF, 3.21 MB

english, 2016

5

[IEEE 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Lisbon, Portugal (2015.5.24-2015.5.27)] 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Fast and robust differential flipflops and their extension to multi-input threshold gates

Yang, Jinghua, Kulkarni, Niranjan, Davis, Joseph, Vrudhula, Sarma

Year:

2015

Language:

english

File:

PDF, 447 KB

english, 2015

6

[IEEE 2017 IEEE International Symposium on Circuits and Systems (ISCAS) - Baltimore, MD, USA (2017.5.28-2017.5.31)] 2017 IEEE International Symposium on Circuits and Systems (ISCAS) - End-to-end scalable FPGA accelerator for deep residual networks

Ma, Yufei, Kim, Minkyu, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

Year:

2017

Language:

english

File:

PDF, 255 KB

english, 2017

7

[IEEE 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Paris, France (2014.7.8-2014.7.10)] 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Integration of threshold logic gates with RRAM devices for energy efficient and robust operation

Yang, Jinghua, Kulkarni, Niranjan, Yu, Shimeng, Vrudhula, Sarma

Year:

2014

Language:

english

File:

PDF, 262 KB

english, 2014

8

[ACM Press the conference - Munich, Germany (2008.03.10-2008.03.14)] Proceedings of the conference on Design, automation and test in Europe - DATE '08 - Current source based standard cell model for accurate signal integrity and timing analysis

Goel, Amit, Vrudhula, Sarma

Year:

2008

Language:

english

File:

PDF, 920 KB

english, 2008

9

[IEEE 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Lisbon, Portugal (2015.5.24-2015.5.27)] 2015 IEEE International Symposium on Circuits and Systems (ISCAS) - Design of threshold logic gates using emerging devices

Vrudhula, Sarma, Kulkami, Niranjan, Yang, Jinghua

Year:

2015

Language:

english

File:

PDF, 773 KB

english, 2015

10

[IEEE 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW) - Seattle, WA, USA (2020.6.14-2020.6.19)] 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW) - Enabling Incremental Knowledge Transfer for Object Detection at the Edge

Farhadi, Mohammad, Ghasemi, Mehdi, Vrudhula, Sarma, Yang, Yezhou

Year:

2020

File:

PDF, 1.16 MB

2020

11

Techniques for estimating test length under random test

Amitava Majumdar, Sarma B. K. Vrudhula

Journal:

Journal of Electronic Testing

Year:

1994

Language:

english

File:

PDF, 1.13 MB

english, 1994

12

[IEEE 2015 IEEE Custom Integrated Circuits Conference - CICC 2015 - San Jose, CA, USA (2015.9.28-2015.9.30)] 2015 IEEE Custom Integrated Circuits Conference (CICC) - Dynamic and leakage power reduction of ASICs using configurable threshold logic gates

Yang, Jinghua, Davis, Joseph, Kulkarni, Niranjan, Seo, Jae-sun, Vrudhula, Sarma

Year:

2015

Language:

english

File:

PDF, 557 KB

english, 2015

13

[IEEE 2016 26th International Conference on Field Programmable Logic and Applications (FPL) - Lausanne, Switzerland (2016.8.29-2016.9.2)] 2016 26th International Conference on Field Programmable Logic and Applications (FPL) - Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

Yufei Ma,, Suda, Naveen, Yu Cao,, Seo, Jae-sun, Vrudhula, Sarma

Year:

2016

Language:

english

File:

PDF, 362 KB

english, 2016

14

[IEEE IEEE Custom Integrated Circuits Conference 2006 - San Jose, CA, USA (2006.09.10-2006.09.13)] IEEE Custom Integrated Circuits Conference 2006 - Predictive Modeling of the NBTI Effect for Reliable Design

Bhardwaj, Sarvesh, Wang, Wenping, Vattikonda, Rakesh, Cao, Yu, Vrudhula, Sarma

Year:

2006

Language:

english

File:

PDF, 2.67 MB

english, 2006

15

[IEEE 2010 International Conference on Microelectronics (ICM) - Cairo, Egypt (2010.12.19-2010.12.22)] 2010 International Conference on Microelectronics - Design of a robust, high performance standard cell threshold logic family for DSM technology

Leshner, Samuel, Kulkarni, Niranjan, Vrudhula, Sarma, Berezowski, Krzysztof

Year:

2010

Language:

english

File:

PDF, 205 KB

english, 2010

16

[IEEE Conference Publications Design, Automation and Test in Europe - Grenoble, France (2015.03.9-2015.03.13)] Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 - Technology-design Co-optimization of Resistive Cross-point Array for Accelerating Learning Algorithms on Chip

Chen, Pai-Yu, Kadetotad, Deepak, Xu, Zihan, Mohanty, Abinash, Lin, Binbin, Ye, Jieping, Vrudhula, Sarma, Seo, Jae-sun, Cao, Yu, Yu, Shimeng

Year:

2015

Language:

english

File:

PDF, 1.81 MB

english, 2015

17

[IEEE 2019 IEEE 37th International Conference on Computer Design (ICCD) - Abu Dhabi, United Arab Emirates (2019.11.17-2019.11.20)] 2019 IEEE 37th International Conference on Computer Design (ICCD) - Threshold Logic in a Flash

Wagle, Ankit, Singh, Gian, Yang, Jinghua, Khatri, Sunil, Vrudhula, Sarma

Year:

2019

File:

PDF, 1.06 MB

2019

18

Performance Modeling for CNN Inference Accelerators on FPGA

Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2019

Language:

english

File:

PDF, 6 KB

english, 2019

19

Thermal aware floorplanning incorporating temperature dependent wire delay estimation

Winther, Andreas Thor, Liu, Wei, Nannarelli, Alberto, Vrudhula, Sarma

Journal:

Microprocessors and Microsystems

Year:

2015

Language:

english

File:

PDF, 761 KB

english, 2015

20

Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors

Hanumaiah, Vinay, Vrudhula, Sarma

Journal:

IEEE Transactions on Computers

Year:

2012

Language:

english

File:

PDF, 1.89 MB

english, 2012

21

[ACM Press the 2001 international symposium - Huntington Beach, California, United States (2001..-..)] Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01 - Time-to-failure estimation for batteries in portable electronic systems

Rakhamtov, Daler, Vrudhula, Sarma

Year:

2001

Language:

english

File:

PDF, 218 KB

english, 2001

22

[ACM Press the 8th ACM/IEEE international workshop - Monterey, California, USA (2002.12.02-2002.12.03)] Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems - TAU '02 - Statistical timing analysis using bounds and selective enumeration

Agarwal, Aseem, Blaauw, David, Zolotov, Vladimir, Vrudhula, Sarma

Year:

2002

Language:

english

File:

PDF, 266 KB

english, 2002

23

[ACM Press the 54th Annual Design Automation Conference 2017 - Austin, TX, USA (2017.06.18-2017.06.22)] Proceedings of the 54th Annual Design Automation Conference 2017 on - DAC '17 - A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits

Kulkarni, Niranjan, Dengi, Aykut, Vrudhula, Sarma

Year:

2017

Language:

english

File:

PDF, 571 KB

english, 2017

24

Spintronic Threshold Logic Array (STLA)—A compact, low leakage, non-volatile gate array architecture

Nukala, Nishant S., Kulkarni, Niranjan, Vrudhula, Sarma

Journal:

Journal of Parallel and Distributed Computing

Year:

2014

Language:

english

File:

PDF, 1.11 MB

english, 2014

25

[IEEE 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Bangalore, India (2007.01.6-2007.01.10)] 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations

Bhardwaj, Sarvesh, Vrudhula, Sarma

Year:

2007

Language:

english

File:

PDF, 234 KB

english, 2007

26

[ACM Press the 42nd annual conference - San Diego, California, USA (2005.06.13-2005.06.17)] Proceedings of the 42nd annual conference on Design automation - DAC '05 - Energy optimal speed control of devices with discrete speed sets

Rao, Ravishankar, Vrudhula, Sarma

Year:

2005

Language:

english

File:

PDF, 783 KB

english, 2005

27

Modeling of Gene Regulatory Network Dynamics Using Threshold Logic

Tejaswi Gowda, Sarma Vrudhula, Seungchan Kim

Journal:

Annals of the New York Academy of Sciences

Year:

2009

Language:

english

File:

PDF, 327 KB

english, 2009

28

[IEEE 37th International Symposium on Multiple-Valued Logic - Oslo, Norway (2007.05.13-2007.05.16)] 37th International Symposium on Multiple-Valued Logic (ISMVL'07) - Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices

Berezowski, Krzysztof S., Vrudhula, Sarma B.K.

Year:

2007

Language:

english

File:

PDF, 280 KB

english, 2007

29

Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity

Xu, Zihan, Mohanty, Abinash, Chen, Pai-Yu, Kadetotad, Deepak, Lin, Binbin, Ye, Jieping, Vrudhula, Sarma, Yu, Shimeng, Seo, Jae-sun, Cao, Yu

Journal:

Procedia Computer Science

Year:

2014

Language:

english

File:

PDF, 927 KB

english, 2014

30

[ACM Press the 41st annual conference - San Diego, CA, USA (2004.06.07-2004.06.11)] Proceedings of the 41st annual conference on Design automation - DAC '04 - A methodology to improve timing yield in the presence of process variations

Raj, Sreeja, Vrudhula, Sarma B. K., Wang, Janet

Year:

2004

Language:

english

File:

PDF, 416 KB

english, 2004

31

[IEEE 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) - San Francisco, CA, USA (2014.6.1-2014.6.5)] 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) - Branch-aware loop mapping on CGRAs

Hamzeh, Mahdi, Shrivastava, Aviral, Vrudhula, Sarma

Year:

2014

Language:

english

File:

PDF, 1.32 MB

english, 2014

32

[IEEE 2017 27th International Conference on Field Programmable Logic and Applications (FPL) - Ghent, Belgium (2017.9.4-2017.9.8)] 2017 27th International Conference on Field Programmable Logic and Applications (FPL) - An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks

Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

Year:

2017

Language:

english

File:

PDF, 1.35 MB

english, 2017

33

[IEEE 2008 Asia and South Pacific Design Automation Conference (ASPDAC) - Seoul, South Korea (2008.03.21-2008.03.24)] 2008 Asia and South Pacific Design Automation Conference - Decomposition based approach for synthesis of multi-level threshold logic circuits

Gowda, Tejaswi, Vrudhula, Sarma

Year:

2008

Language:

english

File:

PDF, 809 KB

english, 2008

34

[IEEE 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Bangalore, India (2007.01.6-2007.01.10)] 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07) - Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations

Vrudhula, Sarma, Bhardwaj, Sarvesh

Year:

2007

Language:

english

File:

PDF, 173 KB

english, 2007

35

[IEEE 2007 European Conference on Circuit Theory and Design (ECCTD 2007) - Sevilla, Spain (2007.08.27-2007.08.30)] 2007 18th European Conference on Circuit Theory and Design - Synthesis of threshold logic circuits using tree matching

Gowda, Tejaswi, Leshner, Samuel, Vrudhula, Sarma, Konjevod, Goran

Year:

2007

Language:

english

File:

PDF, 327 KB

english, 2007

36

Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration

Kadetotad, Deepak, Xu, Zihan, Mohanty, Abinash, Chen, Pai-Yu, Lin, Binbin, Ye, Jieping, Vrudhula, Sarma, Yu, Shimeng, Cao, Yu, Seo, Jae-sun

Journal:

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Year:

2015

Language:

english

File:

PDF, 2.44 MB

english, 2015

37

[ACM Press the 46th Annual Design Automation Conference - San Francisco, California (2009.07.26-2009.07.31)] Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09 - Throughput optimal task allocation under thermal constraints for multi-core processors

Hanumaiah, Vinay, Rao, Ravishankar, Vrudhula, Sarma, Chatha, Karam S.

Year:

2009

Language:

english

File:

PDF, 710 KB

english, 2009

38

[ACM Press the 2012 IEEE/ACM International Symposium - Amsterdam, The Netherlands (2012.07.04-2012.07.06)] Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures - NANOARCH '12 - Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architecture

Nukala, Nishant S., Kulkarni, Niranjan, Vrudhula, Sarma

Year:

2012

Language:

english

File:

PDF, 265 KB

english, 2012

39

[ACM Press the 2006 conference - Yokohama, Japan (2006.01.24-2006.01.27)] Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06 - Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

Bhardwaj, Sarvesh, Cao, Yu, Vrudhula, Sarma

Year:

2006

Language:

english

File:

PDF, 491 KB

english, 2006

40

[IEEE 2014 International Conference on Field-Programmable Technology (FPT) - Shanghai, China (2014.12.10-2014.12.12)] 2014 International Conference on Field-Programmable Technology (FPT) - A fast, energy efficient, field programmable threshold-logic array

Kulkarni, Niranjan, Yang, Jinghua, Vrudhula, Sarma

Year:

2014

Language:

english

File:

PDF, 1.20 MB

english, 2014

41

Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States

Kaviraj Chopra, Sarma Vrudhula

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2006

Language:

english

File:

PDF, 592 KB

english, 2006

42

STEAM

Hanumaiah, Vinay, Desai, Digant, Gaudette, Benjamin, Wu, Carole-Jean, Vrudhula, Sarma

Journal:

ACM Transactions on Embedded Computing Systems

Year:

2014

Language:

english

File:

PDF, 1.74 MB

english, 2014

43

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler

Ma, Yufei, Suda, Naveen, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

Journal:

Integration, the VLSI Journal

Year:

2018

Language:

english

File:

PDF, 3.19 MB

english, 2018

44

Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic

Yang, Jinghua, Dengi, Aykut, Vrudhula, Sarma

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 2.87 MB

english, 2018

45

[ACM Press the 50th Annual Design Automation Conference - Austin, Texas (2013.05.29-2013.06.07)] Proceedings of the 50th Annual Design Automation Conference on - DAC '13 - REGIMap

Hamzeh, Mahdi, Shrivastava, Aviral, Vrudhula, Sarma

Year:

2013

Language:

english

File:

PDF, 1.06 MB

english, 2013

46

[ACM Press the 2007 international symposium - Portland, OR, USA (2007.08.27-2007.08.29)] Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07 - Throughput of multi-core processors under thermal constraints

Rao, Ravishankar, Vrudhula, Sarma, Chakrabarti, Chaitali

Year:

2007

Language:

english

File:

PDF, 221 KB

english, 2007

47

[ACM Press the 43rd annual conference - San Francisco, CA, USA (2006.07.24-2006.07.28)] Proceedings of the 43rd annual conference on Design automation - DAC '06 - High-level power management of embedded systems with application-specific energy cost functions

Cho, Youngjin, Chang, Naehyuck, Chakrabarti, Chaitali, Vrudhula, Sarma

Year:

2006

Language:

english

File:

PDF, 779 KB

english, 2006

48

[ACM Press the 43rd annual conference - San Francisco, CA, USA (2006.07.24-2006.07.28)] Proceedings of the 43rd annual conference on Design automation - DAC '06 - Extending the lifetime of fuel cell based hybrid systems

Zhuo, Jianli, Chakrabarti, Chaitali, Chang, Naehyuck, Vrudhula, Sarma

Year:

2006

Language:

english

File:

PDF, 714 KB

english, 2006

49

On-Chip Sparse Learning Acceleration with CMOS and Resistive Synaptic Devices

Seo, Jae-sun, Lin, Binbin, Kim, Minkyu, Chen, Pai-Yu, Kadetotad, Deepak, Xu, Zihan, Mohanty, Abinash, Vrudhula, Sarma, Yu, Shimeng, Ye, Jieping, Cao, Yu

Journal:

IEEE Transactions on Nanotechnology

Year:

2015

Language:

english

File:

PDF, 3.40 MB

english, 2015

50

[ACM Press the 30th international - Dallas, Texas, United States (1993.06.14-1993.06.18)] Proceedings of the 30th international on Design automation conference - DAC '93 - BDD based decomposition of logic functions with application to FPGA synthesis

Lai, Yung-Te, Pedram, Massoud, Vrudhula, Sarma B. K.

Year:

1993

Language:

english

File:

PDF, 598 KB

english, 1993

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